The invention relates, particularly but not exclusively, to a process for manufacturing electronic semiconductor integrated electronic memory with cells matrix having virtual ground, and throughout the following description, reference will be made to that technical field for convenience of illustration. Discussion of elements or fabrication processes well known to those skilled in the art has been abbreviated or eliminated for brevity.
Electronic semiconductor-integrated EPROM or Flash EPROM memory devices include a plurality of non-volatile memory cells organized in matrix form; that is, the cells are arranged therein into rows, or word lines, and columns, or bit lines.
Each non-volatile memory cell includes a MOS transistor having a floating gate electrode located above the channel region. The floating gate electrode has a high D.C. impedance to all the other terminals of the same cell and the circuit whereto the cell is incorporated.
Each cell also has a second electrode, or control gate, which is driven by means of appropriate control voltages. The other transistor electrodes are, as usual, the drain and source terminals.
In recent years, considerable effort went to the development of memory devices with increased circuit density. This effort resulted in electrically programmable non-volatile memory matrices of the contactless type being developed which have a so-called "tablecloth" or crosspoint structure. An example of matrices of this kind, and their manufacturing process, is described in European Patent No. 0 573 728 of this applicant, incorporated herein by reference.
In matrices of this type, the matrix bit lines are formed in the substrate as continuous parallel diffusion strips. These matrices are formed by memory cells which comprise floating gate capacitive coupling MOS devices.
The process flow for manufacturing such memory cells includes forming, on a semiconductor substrate, mutually parallel stack strips which have a first layer of gate oxide, a layer of first polysilicon, an interpoly oxide layer, and a layer of second polysilicon.
An implantation step is then carried out to form the bit lines, and after the deposition of a planarizing layer, the matrix word lines are formed.
In the prior art, the gate regions of the individual cells are then defined by self-aligned etching. However, this first solution has several drawbacks, one of which is that in cells having small size, the self-aligned etch step becomes more critical.